1. Field of the Invention
The present invention relates to an internal power supply voltage generation circuit for generating an operating power supply voltage used by internal circuitry within a device, and more particularly, to an internal power supply voltage-down converter for down-converting an external power supply voltage to generate an internal power supply voltage as the operating power supply voltage.
2. Description of the Background Art
It is effective to reduce the operating power supply voltage for the purpose of reducing power consumption. With reduction of the power supply voltage, the charging/discharging current of a load capacitance becomes lower. Therefore, reducing the power supply voltage allows the power consumption to be reduced in proportion to the square of the voltage reduction ratio (load resistance such as interconnection resistance is constant). For example, in the case of a general-purpose memory that is widely used, the gate length of a transistor used in internal circuitry is scaled-down to the vicinity of the limit in microminiaturization for each generation for speeding up, to improve the integration density and operation speed. By using an on-chip voltage drop circuit, external power supply voltage is down-converted to generate an internal power supply voltage for the memory. The down-converted internal power supply voltage prevents dielectric breakdown and the like of a microminiaturized transistor, so that higher reliability and lower power consumption by reduction in voltage can be realized. The usage of this on-chip voltage drop circuit allows the externally supplied power supply voltage to be equal to the power supply voltage of an externally provided LSI of general usage. Therefore, a system can be developed with a single power source.
This voltage-drop system is also characterized in that, when the down-converted voltage is set constant at a level sufficiently lower than the external power supply voltage, the constant level is maintained even in the event of variation in the external power supply voltage to allow stable operation of internal circuitry.
FIG. 13 shows an example of a structure of a conventional internal power supply voltage generation circuit. Referring to FIG. 13, a conventional internal power supply voltage generation circuit includes a reference voltage generation circuit RG receiving current from an external power supply node EXV as an external power supply source that supplies externally applied power supply voltage ExtVcc for generating a reference voltage Vref, a subamplifier SA for supplying a current from external power supply node EXV to an internal power supply line IVL according to a result of comparison between reference voltage Vref from reference voltage generation circuit RG and an internal power supply voltage IntVcc on internal power supply line IVL, and a main amplifier MA activated, when an activation control signal ACT that is activated during operation of internal circuitry (not shown) is activated, for supplying current from external power supply node EXV to internal power supply line IVL according to the result of comparison between reference voltage Vref and internal power supply voltage IntVcc.
The current supply ability of main amplifier MA is set sufficiently greater than the current supply ability of subamplifier SA. When internal power supply voltage IntVcc on internal power supply line IVL is consumed during operation of internal circuitry, main amplifier MA operates at high speed to supply a current with great drivability to suppress reduction in internal power supply voltage IntVcc.
Reference voltage generation circuit RG includes a constant current circuit CCS for generating a constant current i independent of external power supply voltage ExtVcc, and a current/voltage converter CVC for converting the current of constant current circuit CCS into voltage to generate reference voltage Vref.
Constant current circuit CCS includes a p channel MOS (insulated gate field effect) transistor P1 connected between external power supply node EXV and a node ND1 and having a gate connected to node ND1, a resistor R having one end connected to external power supply node EXV, a p channel MOS transistor P2 connected between resistor R and a node ND2 and having a gate connected to node ND1, an n channel MOS transistor N1 connected between node ND1 and the ground node and having its gate connected to node ND2, an n channel MOS transistor N2 connected between node ND2 and the ground node and having its gate connected to node ND2, and a p channel MOS transistor P3 for supplying a current from external power supply node EXV according to the level of the voltage on node ND1. MOS transistors N1 and N2 form a current mirror circuit. The absolute value of a threshold voltage VTP1 of MOS transistor P1 is set greater than the absolute value VTP2 of the threshold voltage of MOS transistor P2. The operation will be described.
When MOS transistors N1 and N2 have the same size, a current of the same magnitude flows through MOS transistors N1 and N2. Therefore, a current of the same magnitude also flows through MOS transistors P1 and P2. When MOS transistors P1 and P2 are identical in size, a voltage VR expressed by the following equation is applied across resistor R from the condition that the saturation currents of MOS transistors P1 and P2 are equal to each other. EQU VR=ExtVcc-(.vertline.VTP1.vertline.-.vertline.VTP2 .vertline.)
Therefore, a current IR flowing through resistor R is represented by the following equation. EQU IR=(ExtVcc-VR)/RR=(.vertline.VTP1.vertline.VTP2.vertline.)/RR
RR indicates the resistance of resistor R. MOS transistors P1 and P3 form a current mirror circuit. Therefore, the mirror current of current IR flowing through MOS transistor P1 flows through MOS transistor P3.
MOS transistors P4-P6 receive the ground voltage at respective gates and function as a resistor to generate a voltage according to the current supplied from MOS transistor P3. Therefore, reference voltage Vref has a level determined by the channel resistances of MOS transistors P4-P6 and the threshold voltages of MOS transistors P1 and P2. As a result, reference voltage Vref maintains a constant level independent of external power supply voltage ExtVcc (provided that external power supply voltage ExtVcc is higher than a predetermined voltage level).
Main amplifier MA includes a comparator CMM comparing reference voltage Vref and internal power supply voltage IntVcc on internal power supply line IVL, and a current drive transistor DRM formed of a p channel MOS transistor connected between external power supply node EXV and internal power supply line IVL for supplying a current from external power supply node EXV to internal power supply line IVL in accordance with an output signal from comparator CMM. Comparator CMM includes a p channel MOS transistor P7 connected between external power supply node EXV and a node NDA and having its gate connected to a node NDB, a p channel MOS transistor P8 connected between external power supply node EXV and node NDB and having its gate connected to node NDB, an n channel MOS transistor N3 connected between nodes NDB and NDC and receiving reference voltage Vref at its gate, an n channel MOS transistor N4 connected between nodes NDB and NDC and having its gate connected to internal power supply line IVL, and an n channel MOS transistor N5 connected between the ground node and node NDC and receiving activation control signal ACT at its gate.
Main amplifier MA further includes a p channel MOS transistor P9 connected between external power supply node EXV and the gate of current drive transistor DRM and receiving activation control signal ACT at its gate. The operation of main amplifier MA will be described briefly.
When activation control signal ACT is at an L level (logical low) of an inactive state, MOS transistor 5 is off. The current path of comparator CMM is cut off. Therefore, comparator CMM stops its comparison operation. The gate potential of p channel MOS transistor P9 is at the ground potential level. MOS transistor P9 conducts to electrically connect external power supply node EXV with the gate of current drive transistor DRM. Therefore, current drive transistor DRM is held at an off state. Also, node NDA is held at the level of external power supply voltage by MOS transistor P9. Therefore, when activation control signal ACT is at an inactive state of an L level, the path of the current flow in main amplifier MA is cut off, so that the current is not consumed.
When activation control signal ACT attains an H level (logical high) of an active state (the level of external power supply voltage ExtVcc), MOS transistor N5 is turned on and MOS transistor P9 is turned off. Comparator CMM carries out the comparison operation between reference voltage Vref and internal power supply voltage IntVcc. A signal corresponding to the comparison result is applied to the gate of current drive transistor DRM via node NDA. When reference voltage Vref is higher than internal power supply voltage IntVcc, the conductance of MOS transistor N3 becomes greater than the conductance of MOS transistor N4. As a result, a greater amount of current flows. MOS transistors P7 and P8 form a current mirror circuit with MOS transistor P8 being the master stage. A current of a magnitude identical to that of the current flowing through MOS transistors P8 and N4 is carried through MOS transistors P7 and N3. Therefore, MOS transistor N3 discharges the current applied from MOS transistor P7, whereby the voltage level of node NDA becomes lower. In response, the gate voltage of current drive transistor DRM is reduced. Current drive transistor DRM supplies the current from external power supply node EXV to internal power supply line IVL, whereby the level of internal power supply voltage IntVcc is raised.
In contrast, when internal power supply voltage IntVcc is higher than reference voltage Vref, the conductance of MOS transistor N4 becomes greater than the conductance of MOS transistor N3, so that the current flowing through MOS transistors P8 and N4 increases. MOS transistor N3 cannot discharge all the current supplied from MOS transistor P7. Therefore, the voltage level of node NDA is increased, whereby current drive transistor DRM is turned off. Therefore, when activation control signal ACT is active, main amplifier MA holds internal power supply voltage IntVcc at the level of reference voltage Vref.
Similar to main amplifier MA, subamplifier SA includes a comparator CMS for comparing reference voltage Vref and internal power supply voltage IntVcc, and a current drive transistor DRS formed of a p channel MOS transistor for supplying the current from external power supply node EXV to internal power supply line IVL according to the output signal from comparator CMS. The current drivability of current drive transistor DRS (=maximum drivability) is set smaller than the current drivability of current drive transistor DRM in main amplifier MA (the gate width W/gate length L is set to a small value).
Comparator CMS includes n channel MOS transistors N6 and N7 forming a comparator stage to compare reference voltage Vref and internal power supply voltage IntVcc, and p channel MOS transistors P10 and P11 forming a current mirror type current supply stage for supplying currents respectively to MOS transistors N6 and N7. P channel MOS transistor P11 supplying current to MOS transistor P7 functions as the master stage of the current mirror circuit.
Comparator CMS further includes a current source transistor N8 receiving a voltage BIASL output from node ND2 of reference voltage generation circuit RG at its gate for defining the current flowing through MOS transistors N6 and N7. MOS transistor N8 forms a current mirror with MOS transistor N2 in reference voltage generation circuit RG. The current generated from constant current generation circuit CCS is set small enough to reduce the consumed current. Therefore, the level of bias voltage BIASL is also low, so that the current driven by MOS transistor N8 is small. Therefore, comparator CMS carries out a comparison operation at a relatively small current drivability to supply a current to internal power supply line IVL via current drive transistor DRS.
Subamplifier SA has the function to suppress reduction of internal power supply voltage IntVcc due to leakage current and the like when main amplifier MA is inactive, i.e. when internal circuitry does not operate and is in a standby state. Therefore, the driven amount of current and response rate of subamplifier SA are set to a low level for the purpose of reducing power consumption. Subamplifier SA has its drive current controlled according to bias voltage BIASL, and constantly carries out a comparison operation of reference voltage Vref and internal power supply voltage IntVcc. The gate potential of drive transistor DRS is adjusted according to the comparison result. Therefore, subamplifier SA carries out an operation identical to that of an active main amplifier MA.
MOS transistor P9 suppresses the gate potential of current drive transistor DRAM from becoming unstable when MOS transistors P7 and N3 are turned off so that node NDA attains an electrically floating state in the case where the current path of comparator CMM is cut off in inactivation of activation control signal ACT in main amplifier MA. MOS transistor P9 is provided to reliably drive current drive transistor DRM to an off state when activation control signal ACT is inactive.
FIG. 14 shows the relationship between external power supply voltage ExtVcc and internal power supply voltage IntVcc. When external power supply voltage ExtVcc is low, reference voltage Vref from reference voltage generation circuit RG (refer to FIG. 13) increases in proportion to external power supply voltage ExtVcc. This is because a constant current is not generated in constant current generation circuit CCS when external power supply voltage ExtVcc is low, so that the current supplied by MOS transistor P3 is proportional to external power supply voltage ExtVcc. Therefore, when the level of reference voltage Vref is changed according to external power supply voltage ExtVcc, the level of internal power supply voltage IntVcc also varies according to external power supply voltage ExtVcc. Even when activation control signal ACT is in an inactive state of an L level, the level of internal power supply voltage IntVcc is raised according to the rise of reference voltage Vref because of the operation of subamplifier SA.
When external power supply voltage ExtVcc exceeds a certain voltage level VF, a constant current is conducted stably (at a voltage level where the feedback operation by the current mirror circuit is stabilized) via MOS transistors P1, P2, N1 and N2 in constant current circuit CCS. In response, the current supplied from MOS transistor P3 also becomes constant, so that reference voltage Vref is constant at the level of voltage VF. Even if external power supply voltage ExtVcc rises thereafter, reference voltage Vref is maintained at the constant level of voltage VF. Accordingly, internal power supply voltage IntVcc is also held at the constant level of voltage VF. Thus, as shown in FIG. 14, internal power supply voltage IntVcc varies according to reference voltage Vref, and is held at the constant voltage level in the flat region independently of change in the level of external power supply voltage ExtVcc. Therefore, internal circuitry can operate stably, independent of variation in external power supply voltage ExtVcc.
FIG. 15 shows the relationship between external power supply voltage ExtVcc and internal power supply voltage IntVcc in the actual operation of the circuitry. In the region where the difference between internal power supply voltage IntVcc and external power supply voltage ExtVcc (the difference between reference voltage Vref and external power supply voltage ExtVcc) is small, i.e. in the region near the lower limit of the operating condition, the gain of the internal power supply voltage generation circuit is reduced, as will be described afterwards. As a result, internal power supply voltage IntVcc cannot be raised to the required level of VF even if it is reduced in level at the time of operation of internal circuitry. The level of internal power supply voltage IntVcc will become lower than the voltage level VF of reference voltage Vref. More specifically, particularly in a high speed operation mode where internal circuitry operates at high speed (for example, when the RAS cycle is short and the sense amplifier is repeatedly activated, or when the CAS cycle is short and the internal column related circuitry operates repeatedly at high speed for writing/reading data, in a DRAM), internal power supply voltage IntVcc is consumed so that the voltage level varies in an alternate current manner. When viewed in a direct current manner, internal power supply voltage IntVcc is lower in level than the required voltage level of VF. In the case where external power supply voltage ExtVcc is, for example, 2.5 V corresponding to the lower limit of the operating condition, internal power supply voltage IntVcc is lower approximately by 0.5 V than the required voltage level of 2.0 V. This reduction in the level of internal power supply voltage IntVcc causes degradation in the current drivability of a transistor forming the internal circuitry. It will become difficult for the internal circuitry to operate at high speed. The reason why internal power supply voltage IntVcc becomes lower than the level of reference voltage Vref will be described.
FIG. 16 shows the internal voltage level of main amplifier MA. Activation control signal ACT is changed between the level of external power supply voltage ExtVcc and ground voltage. Current source transistor N5 of comparator CMM in main amplifier MA has its channel length set relatively large to adjust the current consumption in comparator CMM to, for example, approximately 1 to 2 mA. This means that the ON resistance of current source transistor N5 is relatively great, so that the drain voltage of current source transistor N5 is approximately 1.0 V. Current source transistor N5 has its drain connected to the respective sources of MOS transistors N3 and N4. Therefore, even when the conductance of MOS transistor N3 becomes greater than the conductance of MOS transistor N4 so that the voltage level of node NDA is reduced, the voltage level thereof will not become lower than the level of the drain voltage of current source transistor N5. Therefore, node NDA will have a voltage level of 1.0 V at lowest.
Current drive transistor DRM supplies current from external power supply node EXV to internal power supply line IVL, according to the voltage level on node NDA. This current source transistor DRM formed of a p channel MOS transistor supplies current according to the difference between the voltage level of node NDA and the level of the external power supply voltage ExtVcc applied to external power supply node EXV. Therefore, reduction in external power supply voltage ExtVcc causes the gate-source voltage Vgs of current drive transistor DRAM to be further reduced, so that current cannot be supplied at high speed from external power supply node EXV to internal power supply line IVL. As a result, the gain of main amplifier MA is reduced. Therefore, internal power supply voltage IntVcc, when consumed and lowered, cannot be raised to the level of reference voltage Vref. Internal power supply voltage IntVcc will be maintained at a level lower than the level of reference voltage Vref.
Particularly when the difference between external power supply voltage ExtVcc and reference voltage Vref, i.e., internal power supply voltage IntVcc, becomes small, the voltage drop of internal power supply voltage IntVcc at the lower limit of the operating condition shown in FIG. 15 becomes as great as 0.5 V, for example, which is not a negligible level. Thus, there was a problem that internal circuitry cannot be operated at high speed.
Particularly in the case where internal power supply voltage IntVcc is reduced during operation of internal circuitry, external power supply voltage ExtVcc is consumed to compensate for this reduction in internal power supply voltage IntVcc. Therefore, external power supply voltage ExtVcc is reduced in an alternate current manner. When the difference between external power supply voltage ExtVcc and reference voltage Vref becomes smaller, the drop in internal power supply voltage IntVcc becomes greater.
When internal circuitry operates at high speed to charge/discharge a signal line, internal power supply voltage IntVcc is consumed to have the voltage level thereof reduced. Accordingly, the level of external power supply voltage ExtVcc is reduced, so that the drivability of current drive transistor DRM is degraded. As a result, the drop in internal power supply voltage IntVcc becomes greater.
This problem of reduction of internal power supply voltage IntVcc from the level of reference voltage Vref is also encountered in a level shift type voltage down converter that shifts down the level of internal power supply voltage IntVcc for comparison with reference voltage Vref, as well as in a direct feedback type voltage down converter that directly compares internal power supply voltage IntVcc with reference voltage Vref as shown in FIG. 13. This is because the drivability of the current drive transistor is restricted since the gate voltage thereof does not fall down to the level of the ground voltage, reflecting the voltage level of the internal node in the comparator not reduced down to the ground voltage level.